ETH Zurich - D-INFK - IVC - CVG - People - PhD Students - Dominik Honegger

Dominik Honegger


Dominik Honegger

ETH Zürich
Universitätstrasse 6
CH-8092 Zürich

Department of Computer Science
Computer Vision and Geometry Group
CAB G 85.2
CNB D 102.4

+41 (0)44 63 37 269

dominik.honegger@inf.ethz.ch

About Me

I'm a PhD student at the Computer Vision and Geometry Group of the Institute of Visual Computing at the Swiss Federal Institute of Technology Zürich (ETH).

Publications

  • Dominik Honegger, Lorenz Meier, Petri Tanskanen and Marc Pollefeys. An Open Source and Open Hardware Embedded Metric Optical Flow CMOS Camera for Indoor and Outdoor Applications, ICRA2013. (PDF)
  • Dominik Honegger, Pierre Greisen, Lorenz Meier, Petri Tanskanen, and Marc Pollefeys. Real-time Velocity Estimation Based on Optical Flow and Disparity Matching, Proc. IEEE/RSJ Int. Conf. on Intelligent Robots and Systems (IROS), 2012. (PDF)
  • Friedrich Fraundorfer, Lionel Heng, Dominik Honegger, Gim Hee Lee, Lorenz Meier, Petri Tanskanen, and Marc Pollefeys. Vision-Based Autonomous Mapping and Exploration Using a Quadrotor MAV, Proc. IEEE/RSJ Int. Conf. on Intelligent Robots and Systems (IROS), 2012. (PDF)

Videos


IROS 2012 Paper - Autonomous pure vision based exploration




Student Theses

You can do semester, bachelor or master theses as well as D-ITET group projects and D-MAVT focus projects with me.
If you're interested in one of these theses or if you have a suggestion for a thesis in the field of hardware design, please contact me via email.

Current theses:


  • Semester thesis: High Speed 4 Megapixel CameraThe goal of this thesis is to elaborate a frame grabber function for an existing high speed 4 megapixel camera prototype system and implement in a FPGA. Image data from multiple differential links need to be combined to a complete frame and buffered in available DDR2 memory. Afterwards the complete frames should be sent out using an ethernet link to a host computer.
  • Semester thesis: Low Power Hardware AccelerationThe goal of this thesis is to migrate an existing stereo matching and optical flow FPGA implementation from an Altera Cyclone III FPGA to a latest generation Xilinx FPGA. Vendor specific hardware blocks need to be adjusted. The physical camera interfaces should be changed from parallel to high speed differential signaling (LVDS).

Teaching Assistant

  • Lineare Algebra (D-INFK) — HS2012
  • Informatik I (D-MAVT) — FS2013

© CVG, ETH Zürich dominik.honegger@inf.ethz.ch