Modeling and Simulation of Digital Circuits in Dymola/Modelica

Description

Dymola is the most advanced software on the market today for the modeling and simulation of physical systems. Dymola ist fully object-oriented, and offers the user a graphical interface that permits modeling even highly complex systems in such a way as to make the resulting models easily maintainable [1].

For this reason, Dymola is very well suited for modeling electronic circuits. Whereas the modeling of analog electronic circuits is already supported fairly well in Dymola [2], the available support for modeling digital electronic circuits still leaves to be desired.

It is the goal of this project to develop functional Dymola/Modelica libraries for modeling digital electronic circuits. These libraries shall make it possible to simulate such circuits either at the transistor level, the gate level, or the chip level. It is a further goal to make these libraries compatible with each other, such that large digital circuits can be simulated digitally, whereas individual sub-circuits that are of particular concern to the modeler, can be simulated in an analog fashion.

Tasks to be tackled

The first task is to develop a general-purpose digital electronic library for modeling at the gate level. This library is supposed to use the conventional digital gate symbols for their iconic representation. Furthermore, it is necessary that the gate delay, the fanin, and the fanout of the gates are considered, such that spikes that can occur in the circuit be shown by the simulations. Compare your solution with LogicWorks [3], a software tool that has been designed specially for the simulation of digital electronic circuits.

The above library shall then be enhanced by models that can simulate the most widely used logic chips. Also for this task, LogicWorks may be used as a reference.

We furthermore wish to create a special library for a given family of logic circuit chips, e.g. TTL or ECL. This library uses the same models as the general library. However, its model parameters are fixed by the chosen family, and can no longer be set by the user.

Design also an analog electronic library that models a selected family of logic gates (e.g. TTL or ECL) at the transistor level. This library shall be based on the BondLib library [2,4]. The library shall furthermore offer interface models that make it possible to incorporate such analog components within a digital circuit.

References

  1. Brück, D., H. Elmqvist, H. Olsson, S.E. Mattsson (2002), Dymola for Multi-Engineering Modeling and Simulation, Proc. 2nd International Modelica Conference, Oberpfaffenhofen, Germany, pp. 55:1-55:8.

  2. Cellier, F.E., C. Clauß and A. Urquía (2007), Electronic Circuit Modeling and Simulation in Modelica, Proc. 6th Eurosim Congress on Modelling and Simulation, Ljubljana, Slovenia, Vol.2, pp. 1-10.

  3. Capilano Computing Systems (2002), LogicWorks 4: Interactive Circuit Design Software, Capilano Computing Systems, Ltd.

  4. Cellier, F.E. and A. Nebot (2005), The Modelica Bond Graph Library, Proc. 4th International Modelica Conference, Hamburg, Germany, Vol.1, pp. 57-65.
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Last modified: October 8, 2007 -- © François Cellier