Hi there! I am a third-year doctoral student supervised by Timothy Roscoe (Mothy) in the Systems Group at ETH Zurich.
I am working on the management of caches and shared memory for emerging interconnect standards like CXL. These interconnects allow us to directly share large pools of memory across multiple independent machines, introducing interesting challenges related to caching:
For the bulk of these shared memory pools, the caches of the individual machines will be non-coherent due to hardware resource limitations. Correctly managing non-coherent caches in software is challenging: Modern memory consistency models all assume hardware cache coherence. Its absence fundamentally breaks our intuition about shared memory, along with most primitives and abstractions we rely on. I am currently developing a set of new primitives to manage non-coherence, focusing on in-memory databases as initial target applications.
For small regions of shared memory, global coherence can be maintained in hardware. However, this requires that the different implementations of the interconnect standard's coherence protocol interoperate correctly. Previously, I have investigated how exhaustive conformance testing can be applied post-silicon to assert that a given cache coherence implementation conforms to the interconnect standard's protocol specification.
I am thrilled to be a part of the Enzian project, which serves both as inspiration and main experimental platform for my work. Enzian coherently attaches a Xilinx FPGA to Cavium's ThunderX1 CPU by leveraging the latter's native NUMA cache coherence protocol. During the development of our initial FPGA-side protocol implementation, we have experienced the interoperability challenges of coherent interconnects first-hand. Since the FPGA-side protocol remains fully reconfigurable, the Enzian platform is uniquely suited to the study of future cache coherent as well as non-coherent systems.
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