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Scalable Memory Systems (HiPEAC ACACES Summer School 2013)
This is the webpage that hosts the materials (both preliminary and final) for the Scalable Many-Core Memory Systems course I taught at HiPEAC ACACES Summer School during July 15-19, 2013.
Course Abstract
Link to course abstract at HiPEAC page
The memory system is a fundamental performance and energy bottleneck
in almost all computing systems. Recent trends towards increasingly
more cores on die, consolidation of diverse workloads on a single
chip, and difficulty of DRAM scaling impose new requirements and
exacerbate old demands on the memory system. In particular, the need
for memory bandwidth and capacity is increasing, applications'
interference in memory system increasingly limits system performance
and makes the system hard to control, memory energy and power are key
design concerns, and DRAM technology consumes significant amounts of
energy and does not scale down easily to smaller technology
nodes. Fortunately, some promising solution directions exist. In this
short course, we will first briefly cover basics of memory systems and
examine fundamental tradeoffs. Next, we will describe recent
technology, application, and architecture trends and how they change
the way we should think of and design memory systems. Finally, we will
examine new memory system designs for multi-core architectures to
address these trends and requirements. In particular, we will cover
recent research on tackling challenges related to scaling the
capacity, energy-efficiency, bandwidth, latency, and feature size of
main memory. We will potentially examine three major solution
directions: 1) how to design more efficient and higher-bandwidth DRAM
architectures, 2) how to employ emerging memory technologies in a
hybrid memory system, and 3) how to enable more predictable and
QoS-aware memory systems.
Overview Reading
The reading below is strongly recommended for attendees of the
course. Lectures will revolve around the topics outlined in this
5-page paper. I also encourage you to go through the slides associated
with this paper.
Final Slides and Videos
The following are the slides that were covered in each lecture.
Preliminary Slides
The following are the tentative set of slides we provided before the course. Note that not all slides were actually covered. Refer to final slides above for what was actually covered.
The slides include links and references to readings and videos associated with each topic.
We will cover three major topics:
- Topic 1: DRAM Basics and DRAM Scaling (pptx) (pdf)
- Topic 2: Emerging Technologies and Hybrid Memories (pptx) (pdf)
- Topic 3: Memory Interference and QoS-Aware Memory Systems (pptx) (pdf)
We will likely not cover the following two major topics, but the below
slides are provided for your benefit. These would likely be useful in
putting everything into the entire system perspective.
Links to Background Lecture Videos
You may find the following lecture videos useful as background information:
- Memory Hierarchy (and Introduction to Caches) (video)
- Main Memory (video)
- Memory Controllers, Memory Scheduling, Memory QoS (video 1) (video 2)
- Multiprocessor Correctness and Cache Coherence (video)
- Emerging Memory Technologies (video)
The following lecture videos can also be useful if you would like to study the optional topics:
Finally, if you wish, you can study the entire set of videos that cover a wide range of topics in computer architecture:
Extended Reading List
Most of the readings we will touch on are provided in the preliminary slides above. You can find most readings here.
As time permits, other covered or mentioned readings will be provided on this page as well.
Readings for Topic 1 (DRAM Basics and DRAM Scaling)
-
Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu,
"Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture"
Proceedings of the 19th International Symposium on High-Performance Computer
Architecture (HPCA), Shenzhen, China, February 2013. Slides (pptx)
-
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu,
"A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM"
Proceedings of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.
Slides (pptx)
-
Jamie Liu, Ben Jaiyen, Richard Veras, and Onur Mutlu,
"RAIDR: Retention-Aware Intelligent DRAM Refresh"
Proceedings of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.
Slides (pdf)
-
Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and Onur Mutlu,
"An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms"
Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013.
Slides (pptx) Slides (pdf)
- Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry,
"RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data"
CMU Computer Science Technical Report, CMU-CS-13-108, Carnegie Mellon University, April 2013.
- Engin Ipek, Onur Mutlu, José F. Martínez, and Rich Caruana,
"Self Optimizing Memory Controllers: A Reinforcement Learning Approach"
Proceedings of the 35th International Symposium on
Computer Architecture (ISCA), pages 39-50, Beijing, China, June 2008. Slides (pptx)
- Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,
"DRAM-Aware Last-Level Cache
Writeback: Reducing Write-Caused Interference in Memory
Systems"
HPS Technical Report, TR-HPS-2010-002,
April 2010.
-
Howard David, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, and Onur Mutlu,
"Memory Power Management via Dynamic Voltage/Frequency Scaling"
Proceedings of the 8th International Conference on Autonomic Computing (ICAC), Karlsruhe, Germany, June 2011.
Slides (pptx) (pdf)
Readings for Topic 2 (Emerging Technologies and Hybrid Memories)
- Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger,
"Architecting Phase Change Memory as a Scalable DRAM Alternative"
Proceedings of the 36th International Symposium on
Computer Architecture (ISCA), pages 2-13, Austin, TX, June 2009.
Slides (pdf)
One of the 13 computer architecture papers
of 2009 selected as Top Picks by IEEE Micro.
Selected as a CACM
Research Highlight.
- Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, and Doug Burger,
"Phase Change Technology and the Future of Main Memory"
IEEE Micro,
Special Issue: Micro's Top Picks from 2009 Computer Architecture
Conferences (MICRO TOP PICKS), Vol. 30, No. 1, pages
60-70, January/February 2010.
- HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, and Onur Mutlu,
"Row Buffer Locality Aware Caching Policies for Hybrid Memories"
Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), Montreal, Quebec, Canada, September 2012.
Slides (pptx) (pdf)
Best paper award (in Computer Systems and Applications track).
-
Justin Meza, Jichuan Chang, HanBin Yoon, Onur Mutlu, and Parthasarathy Ranganathan,
"Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management"
IEEE Computer Architecture Letters (CAL), February 2012.
-
Justin Meza, Yixin Luo, Samira Khan, Jishen Zhao, Yuan Xie, and Onur Mutlu,
"A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory"
Proceedings of the 5th Workshop on Energy-Efficient Design (WEED), Tel-Aviv, Israel, June 2013.
Slides (pptx) Slides (pdf)
-
Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrian Cristal, Osman Unsal, and Ken Mai,
"Error Analysis and Retention-Aware Error Management for NAND Flash Memory"
Intel Technology Journal (ITJ) Special Issue on Memory Resiliency, Vol. 17, No. 1, May 2013.
-
Emre Kultursay, Mahmut Kandemir, Anand Sivasubramaniam, and Onur Mutlu,
"Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative"
Proceedings of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, April 2013.
Slides (pptx) (pdf)
Readings for Topic 3 (Memory Interference and QoS-Aware Memory Systems)
- Thomas Moscibroda and Onur
Mutlu,
"Memory Performance Attacks: Denial of Memory Service in
Multi-Core Systems"
Proceedings of the 16th USENIX Security Symposium
(USENIX SECURITY), pages 257-274, Boston, MA, August 2007.
Slides (ppt)
- Onur
Mutlu and Thomas Moscibroda,
"Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors"
Proceedings of the 40th International Symposium on
Microarchitecture (MICRO), pages 146-158, Chicago, IL, December 2007. Slides (ppt)
- Onur Mutlu and Thomas Moscibroda,
"Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems"
Proceedings of the 35th International Symposium on
Computer Architecture (ISCA), pages 63-74, Beijing, China, June 2008. Slides (ppt)
One of the 12 computer architecture papers
of 2008 selected as Top Picks by IEEE Micro.
- Onur Mutlu and Thomas Moscibroda,
"Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers"
IEEE
Micro, Special Issue: Micro's Top Picks from 2008 Computer Architecture
Conferences (MICRO TOP PICKS), Vol. 29, No. 1, pages 22-32, January/February 2009.
- Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter,
"ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers"
Proceedings of the 16th International Symposium on High-Performance Computer
Architecture (HPCA), Bangalore, India, January 2010.
Slides (pptx)
Best paper session. One of the four papers nominated for the
Best Paper Award by the Program Committee.
- Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter,
"Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior"
Proceedings of the 43rd International Symposium on Microarchitecture (MICRO), pages 65-76, Atlanta, GA, December 2010.
Slides (pptx) (pdf)
One of the 11 computer architecture papers
of 2010 selected as Top Picks by IEEE Micro.
- Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter,
"Thread Cluster Memory Scheduling"
IEEE
Micro, Special Issue: Micro's Top Picks from 2010 Computer Architecture
Conferences (MICRO TOP PICKS), Vol. 31, No. 1, pages 78-89, January/February 2011.
-
Rachata Ausavarungnirun, Kevin Chang, Lavanya Subramanian, Gabriel Loh, and Onur Mutlu,
"Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems"
Proceedings of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012.
Slides (pptx)
- Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
"Parallel Application Memory Scheduling"
Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011.
Slides (pptx)
-
Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, and Onur Mutlu,
"MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems"
Proceedings of the 19th International Symposium on High-Performance Computer
Architecture (HPCA), Shenzhen, China, February 2013. Slides (pptx)
- Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda,
"Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning"
Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011.
Slides (pptx)
- Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
"Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems"
Proceedings of the 15th International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS), pages 335-346, Pittsburgh, PA, March 2010.
Slides (pdf)
Best paper award.
-
Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, and Mani Azimi,
"Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems"
Proceedings of the 19th International Symposium on High-Performance Computer
Architecture (HPCA), Shenzhen, China, February 2013. Slides (pptx)
- Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt,
"Prefetch-Aware Memory Controllers"
IEEE Transactions on Computers (TC), Vol. 60, No. 10, pages 1406-1430, October 2011.
-
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
"Prefetch-Aware Shared Resource Management for Multi-Core Systems"
Proceedings of the 38th International Symposium on Computer Architecture (ISCA), San Jose, CA, June 2011.
Slides (pptx)