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Honors and Awards

Google Faculty Research Award, 2016.

Best paper session at MICRO 2016.
         "Continuous Runahead: Transparent Hardware Acceleration for Memory Intensive Workloads"    Slides (pptx) (pdf)

Google Faculty Research Award, 2015.

Best paper runner-up at HPCA 2015.
         Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery    Slides (pptx) (pdf)

Best (student) presentation award at HiPEAC 2015.
         Efficient Data Mapping and Buffering Techniques for Multi-Level Cell Phase-Change Memories    Slides (ppt) (pdf)

Google Faculty Research Award, 2014.

Microsoft Research Software Engineering Innovation Foundation (SEIF) Award, 2014.

Best paper award at RTAS 2014.
         Bounding Memory Interference Delay in COTS-based Multi-Core Systems    Slides (pptx) (pdf)

Best Paper Session at HPCA 2014.
         Improving Cache Performance by Exploiting Read-Write Disparity    Slides (pptx) (pdf)

Dr. William D. and Nancy W. Strecker Early Career Professorship, January 2013.

IBM Faculty Partnership Award, 2013.

Intel Early Career Faculty Honor Program Award, 2012.

IEEE Computer Society Technical Committee on Computer Architecture Young Computer Architect Award, 2011.

Carnegie Mellon University College of Engineering George Tallman Ladd Research Award, 2012.

IBM Faculty Partnership Award, 2012.

Hewlett-Packard Laboratories Innovation Research Program Award, 2012.

Nvidia CUDA Center of Excellence Award, 2012. (Center led by Kayvon Fatahalian)

Best paper award at ICCD 2012 (Computer Systems and Applications Track), 2012.
         Row Buffer Locality Aware Caching Policies for Hybrid Memories    Slides (pptx) (pdf)

Best paper award at ASPLOS 2010.
         Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems    Slides (pdf)

Best paper award at VTS 2010 (awarded in 2011).
         Concurrent Autonomous Self-Test for Uncore Components in System-on-Chips    Slides (ppt)

One paper (of 12 total) selected for IEEE Micro's "Top Picks from Computer Architecture Conferences," 2011.
         Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees    Slides (pptx)

Three papers (of 11 total) selected for IEEE Micro's "Top Picks from Computer Architecture Conferences," 2010.
         Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior    Slides (pptx) (pdf)
         Aergia: Exploiting Packet Latency Slack in On-Chip Networks    Slides (pptx)
         Data Marshaling for Multi-core Architectures    Slides (ppt)

Two papers (of 13 total) selected for IEEE Micro's "Top Picks from Computer Architecture Conferences," 2009.
         Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures    Slides (ppt)
         Architecting Phase Change Memory as a Scalable DRAM Alternative    Slides (pdf)

One paper (of 12 total) selected for IEEE Micro's "Top Picks from Computer Architecture Conferences," 2008.
         Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers    Slides (ppt)

One paper (of 11 total) selected for IEEE Micro's "Top Picks from Computer Architecture Conferences," 2006.
         Diverge-Merge Processor (DMP): Generalized and Energy-Efficient Dynamic Predication    Slides (ppt)

Two papers (of 13 total) selected for IEEE Micro's "Top Picks from Computer Architecture Conferences," 2005.
         Efficient Runahead Execution: Power-efficient Memory Latency Tolerance    Slides (ppt)
         Wish Branches: Enabling Adaptive and Aggressive Predicated Execution    Slides (ppt)

One paper (of 15 total) selected for IEEE Micro's "Top Picks from Computer Architecture Conferences," 2003.
         Runahead Execution: An Effective Alternative to Large Instruction Windows    Slides (pdf)

One paper selected for CACM's "Research Highlights," 2009.
         Architecting Phase Change Memory as a Scalable DRAM Alternative    Slides (pdf)

Best Paper Session at HPCA 2010.
         ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers    Slides (pptx)

Best Paper Session at HPCA 2009.
         Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems    Slides (ppt)

Best paper award nominations at NOCS 2012, HPCA 2010, HPCA 2009, HPCA 2007, MICRO 2006, and MICRO 2005 conferences.

Selected to the ISCA Hall of Fame, 2009.

Selected to the MICRO Hall of Fame, 2009.

NSF CAREER Award, 2010.
         QoS-Aware, High-Performance, and Scalable Many-Core Memory Systems

Microsoft Gold Star Award, 2008.

PhD Dissertation nominated by UT-Austin for the ACM Doctoral Dissertation Award, 2006.

University Co-op/George H. Mitchell Award for Excellence in Graduate Research (Awarded to 6 out of 271 nominees at UT-Austin), 2005.

Intel Foundation Ph.D. Fellowship, 2004.

University of Texas Graduate School Continuing Fellowship, 2003.

University of Michigan EECS Dept. Summer Research Fellowship, 1999, 2000.

University of Michigan EECS Dept. William Harvey Seeley Award (award given to the top undergraduate junior), 1999.

University of Michigan Branstrom Freshman Prize, 1998.